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bus_ctrl.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
3/*
4 * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _HARDWARE_STRUCTS_BUS_CTRL_H
10#define _HARDWARE_STRUCTS_BUS_CTRL_H
11
13#include "hardware/regs/busctrl.h"
14
15// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
16//
17// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
18// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.
19//
20// Bit-field descriptions are of the form:
21// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
22
23enum bus_ctrl_perf_counter {
24 arbiter_rom_perf_event_access = 19,
25 arbiter_rom_perf_event_access_contested = 18,
26 arbiter_xip_main_perf_event_access = 17,
27 arbiter_xip_main_perf_event_access_contested = 16,
28 arbiter_sram0_perf_event_access = 15,
29 arbiter_sram0_perf_event_access_contested = 14,
30 arbiter_sram1_perf_event_access = 13,
31 arbiter_sram1_perf_event_access_contested = 12,
32 arbiter_sram2_perf_event_access = 11,
33 arbiter_sram2_perf_event_access_contested = 10,
34 arbiter_sram3_perf_event_access = 9,
35 arbiter_sram3_perf_event_access_contested = 8,
36 arbiter_sram4_perf_event_access = 7,
37 arbiter_sram4_perf_event_access_contested = 6,
38 arbiter_sram5_perf_event_access = 5,
39 arbiter_sram5_perf_event_access_contested = 4,
40 arbiter_fastperi_perf_event_access = 3,
41 arbiter_fastperi_perf_event_access_contested = 2,
42 arbiter_apb_perf_event_access = 1,
43 arbiter_apb_perf_event_access_contested = 0
44};
45
46typedef struct {
47 _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0
48 // Bus fabric performance counter 0
49 // 0x00ffffff [23:0] : PERFCTR0 (0): Busfabric saturating performance counter 0
50 io_rw_32 value;
51
52 _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0
53 // Bus fabric performance event select for PERFCTR0
54 // 0x0000001f [4:0] : PERFSEL0 (0x1f): Select an event for PERFCTR0
55 io_rw_32 sel;
57
58typedef struct {
59 _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY
60 // Set the priority of each master for bus arbitration
61 // 0x00001000 [12] : DMA_W (0): 0 - low priority, 1 - high priority
62 // 0x00000100 [8] : DMA_R (0): 0 - low priority, 1 - high priority
63 // 0x00000010 [4] : PROC1 (0): 0 - low priority, 1 - high priority
64 // 0x00000001 [0] : PROC0 (0): 0 - low priority, 1 - high priority
65 io_rw_32 priority;
66
67 _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK
68 // Bus priority acknowledge
69 // 0x00000001 [0] : BUS_PRIORITY_ACK (0): Goes to 1 once all arbiters have registered the new global priority levels
70 io_ro_32 priority_ack;
71
72 bus_ctrl_perf_hw_t counter[4];
74
75#define bus_ctrl_hw ((bus_ctrl_hw_t *)BUSCTRL_BASE)
76
77#endif
Definition bus_ctrl.h:58
Definition bus_ctrl.h:46